Bulldozer Copy 1.2 Free

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Marvin John Heemeyer (October 28, 1951 – June 4, 2004) was an American welder and an automobile muffler repair shop owner who demolished numerous buildings with a modified bulldozer in Granby, Colorado on June 4, 2004. Bulldozer Classic free download - Media Player Classic Home Cinema, Backgammon Classic, Media Player Classic Home Cinema (64-bit), and many more programs. 9,623 Bulldozer clip art images on GoGraph. Download high quality Bulldozer clip art from our collection of 41,940,205 clip art graphics. Bulldozer Mania free download - Elasto Mania - Elastomaniac.com level pack 2, TrackMania Sunrise, Zoo Tycoon 2: Marine Mania demo, and many more programs. 9,623 Bulldozer clip art images on GoGraph. Download high quality Bulldozer clip art from our collection of 41,940,205 clip art graphics.

Excavator – Family 15h (4th-gen)
Produced2015
Common manufacturer(s)
Min. feature size28 nm bulk silicon (GF28A)[1]
Instruction setAMD64 (x86-64)
Core name(s)
PredecessorSteamroller – Family 15h (3rd-gen)
SuccessorZen

AMD Excavator Family 15h is a microarchitecture developed by AMD to succeed Steamroller Family 15h for use in AMD APU processors. On October 12, 2011, AMD revealed Excavator to be the code name for the fourth-generation Bulldozer-derived core.

The Excavator-based APU for mainstream applications is called Carrizo and was released in 2015.[2][3]The Carrizo APU is designed to be HSA 1.0 compliant.[4]An Excavator-based APU and CPU variant named Toronto for server and enterprise markets will also be available.[5]

Excavator has been confirmed to be AMD's final revision of the 'Bulldozer' family, with two new microarchitectures replacing Excavator a year later.[6][7]The next generation sister architectures will be the x86-64Zen and AArch64K12 architectures.[8][9]

  • 2Processors
    • 2.1APU lines

Architecture[edit]

Excavator added hardware support for new instructions such as AVX2, BMI2 and RdRand.[10]Excavator is designed using High Density (aka 'Thin') Libraries normally used for GPUs to reduce electric energy consumption and die size, delivering a 30 percent increase in efficient energy use.[11] Excavator can process up to 15% more instructions per clock compared to AMD's previous core Steamroller.[12]

Processors[edit]

APU lines[edit]

Main article: List of AMD Accelerated Processing Unit microprocessors

There are three APU lines announced or released:

  1. Budget and mainstream markets (mobile only): Carrizo APU
    • The Carrizo mobile APUs were launched in 2015 based on Excavator x86 cores and featuring Heterogeneous System Architecture for integrated task sharing between CPUs and GPUs, which allows a GPU to perform compute functions, which is claimed provide greater performance increases than shrinking the feature size alone.[4]
  2. Budget and mainstream markets (desktop and mobile): Bristol Ridge, and Stoney Ridge (for entry level notebooks), APUs[13]
    • Bristol Ridge APUs utilize socket AM4 and DDR4 RAM
    • Bristol Ridge APUs have up to 4 Excavator CPU cores and up to 8 3rd generation GCN GPU cores
    • Up to a 20% CPU performance increase over Carrizo
    • TDP of 15W to 65W, 15–35W for mobile
  3. Enterprise and server markets: Toronto APU
    • The Toronto APU for server and enterprise markets featured four x86 Excavator CPU core modules and Volcanic Islands integrated GPU core.
    • The Excavator four modular cores has a greater advantage with IPC than Steamroller. The improvement is 4–15%.
    • Support for HSA/hUMA, DDR3/DDR4, PCIe 3.0, GCN 1.2[4][5][9]
    • The Toronto APU was available in BGA and SoC variants. The SoC variant had the southbridge on the same die as the APU to save space and power and to optimize workloads.
    • A complete system with a Toronto APU would have a maximum power usage of 70 W.[5]

CPU Desktop lines[edit]

There are no plans for Steamroller (3rd gen Bulldozer) or Excavator (4th gen Bulldozer) architectures on high-end desktop platforms.

Excavator CPU for Desktop announced on 2nd Feb 2016, named Athlon X4 845.[14]

Athlon X4 845 vs 860K comparison
CPU modelFrequency (GHz)CoresTDP (Watt)L1D cacheL2 cachePCI Express 3.0Relative IPC
Athlon X4 845 (Carrizo)3.5 (3.8 turbo)4654*32KB2*1MBX81.05–1.15
Athlon X4 860K (Kaveri)3.7 (4.0 turbo)4954*16KB2*2MBX161.0

Server lines[edit]

The AMD Opteron roadmaps for 2015 show the Excavator-based Toronto APU and Toronto CPU intended for 1 Processor (1P) cluster applications:[5]

  • For 1P Web and Enterprise Services Clusters:
    • Toronto CPU – quad-core x86 Excavator architecture
    • plans for Cambridge CPU – 64-bit AArch64 core
  • For 1P Compute and Media Clusters:
    • Toronto APU – quad-core x86 Excavator architecture
  • For 2P/4P Servers:
    • Warsaw CPU – 12/16 core x86 Piledriver (2nd gen Bulldozer) (Opteron 6338P and 6370P)
    • no plans for Steamroller (3rd gen Bulldozer) or Excavator (4th gen Bulldozer) architectures on high-end multi-processor platforms

References[edit]

  1. ^http://www.extremetech.com/computing/176919-amd-leak-confirms-that-excavator-apu-will-be-28nm-and-that-some-production-is-moving-back-to-globalfoundries
  2. ^Reynolds, Sam (October 31, 2013). 'New confirmed details on AMD's 2014 APU lineup, Kaveri delayed'. Vr-zone.com. Retrieved November 24, 2013.
  3. ^'AMD updates product roadmap for 2014 and 2015'. Digitimes.com. August 26, 2013. Retrieved November 24, 2013.
  4. ^ abcHachman, Mark (November 21, 2014). 'AMD reveals high-end 'Carrizo' APU, the first chip to fully embrace audacious HSA tech'. PCWorld. Retrieved January 15, 2015.
  5. ^ abcdMujtaba, Hassan (December 26, 2013). 'AMD Opteron Roadmap Reveals Next Generation Toronto and Carrizo APU Details'. WCCF Tech. Retrieved January 15, 2015.
  6. ^http://www.bit-tech.net/news/hardware/2014/09/11/amd-zen/1
  7. ^'Archived copy'. Archived from the original on 2014-05-13. Retrieved 2014-05-22.CS1 maint: Archived copy as title (link)
  8. ^Moammer, Khalid (September 9, 2014). 'AMD's Next Gen x86 High Performance Core is Zen'. WCCF Tech. Retrieved January 15, 2015.
  9. ^ abMujtaba, Hassan (May 5, 2014). 'AMD Announces 2014-2016 Roadmap – 20nm Project SkyBridge and K12 64-bit ARM Cores For 2016'. WCCF Tech. Retrieved January 15, 2015.
  10. ^'AMDs Carrizo architecture detailed and explored'. Extremetech.com. June 2, 2015. Retrieved March 3, 2019.
  11. ^http://www.tomshardware.com/news/Steamroller-High_Density_Libraries-hot-chips-cpu-gpu,17218.html
  12. ^http://wccftech.com/amd-carrizo-apu-architecture-hot-chips/
  13. ^Cutress, Ian (1 June 2016). 'AMD Announces 7th Generation APU'. Anandtech.com. Retrieved 1 June 2016.
  14. ^Jeff Kampman (2 February 2016). 'AMD puts Excavator on the desktop with the Athlon X4 845'.
Retrieved from 'https://en.wikipedia.org/w/index.php?title=Excavator_(microarchitecture)&oldid=886015190'
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Bulldozer Copy 1.2 Free
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Bulldozer - Family 15h
ProducedFrom late 2011 to present
Common manufacturer(s)
Min. feature size32 nm
Instruction setx86-64
Core name(s)
Socket(s)
PredecessorFamily 10h (K10)
SuccessorPiledriver - Family 15h (2nd-gen)

The AMD Bulldozer Family 15h is a microprocessormicroarchitecture for the FX and Opteron line of processors, developed by AMD for the desktop and server markets.[1][2] Bulldozer is the codename for this family of microarchitectures. It was released on October 12, 2011, as the successor to the K10 microarchitecture.

Bulldozer copy 1.2 free full

Bulldozer is designed from scratch, not a development of earlier processors.[3] The core is specifically aimed at computing products with TDPs of 10 to 125 watts. AMD claims dramatic performance-per-watt efficiency improvements in high-performance computing (HPC) applications with Bulldozer cores.

The Bulldozer cores support most of the instruction sets implemented by Intel processors available at its introduction (including SSE4.1, SSE4.2, AES, CLMUL, and AVX) as well as new instruction sets proposed by AMD; ABM, XOP, FMA4 and F16C.[4][5]

  • 2Architecture
  • 3Processors
  • 5Performance

Overview[edit]

Bulldozer

According to AMD, Bulldozer-based CPUs are based on GlobalFoundries' 32 nm Silicon on insulator (SOI) process technology and reuses the approach of DEC for multitasking computer performance with the arguments that it, according to press notes, 'balances dedicated and shared computer resources to provide a highly compact, high units count design that is easily replicated on a chip for performance scaling.'[6] In other words, by eliminating some of the 'redundant' elements that naturally creep into multicore designs, AMD has hoped to take better advantage of its hardware capabilities, while using less power.

Bulldozer-based implementations built on 32nm SOI with HKMG arrived in October 2011 for both servers and desktops. The server segment included the dual chip (16-core) Opteron processor codenamed Interlagos (for Socket G34) and single chip (4, 6 or 8 cores) Valencia (for Socket C32), while the Zambezi (4, 6 and 8 cores) targeted desktops on Socket AM3+.[7][8]

Bulldozer Copy 1.2 Free Download

Bulldozer is the first major redesign of AMD’s processor architecture since 2003, when the firm launched its K8 processors, and also features two 128-bit FMA-capable FPUs which can be combined into one 256-bit FPU. This design is accompanied by two integer clusters, each with 4 pipelines (the fetch/decode stage is shared). Bulldozer also introduced shared L2 cache in the new architecture. AMD calls this design a 'Module'. A 16-core processor design would feature eight of these 'modules',[9] but the operating system will recognize each 'module' as two logical cores.

The modular architecture consists of multithreaded shared L2 cache and FlexFPU, which uses simultaneous multithreading. Each physical integer core, two per module, is single threaded, in contrast with Intel's Hyperthreading, where two virtual simultaneous threads share the resources of a single physical core.[10][11]

Architecture[edit]

Bulldozer core[edit]

Block diagram of a complete Bulldozer module, showing 2 integer clusters
Block diagram of a 4 module design with 8 integer clusters

Bulldozer introduced a 'Clustered MultiThreading' (CMT) where some parts of the processor are shared between two threads and some parts are unique for each thread. Discrete mathematics solutions pdf.

Bulldozer copy 1.2 free download

In terms of hardware complexity and functionality, the Bulldozer CMT module is equal to a dual-core processor in its integer power, and to either a single-core processor or a dual core in its floating-point power, depending on whether the code is saturated in floating point instructions in both threads running on the same CMT module, and whether the FPU is performing 128-bit or 256-bit floating point operations. The reason for this is that for each two integer cores, there is a floating-point unit consisting of a pair of 128-bit FMACexecution units.

CMT is a simpler but similar design philosophy to SMT; both designs try to utilize execution units efficiently; in either method, when two threads compete for some execution pipelines, there is a loss in performance in one or more of the threads. Due to dedicated integer cores, the Bulldozer family modules performed roughly like a dual core dual thread processor during sections of code that were either wholly integer or a mix of integer and floating point; yet, due to the SMT use of the shared floating point pipelines, the module would perform similarly to a single core dual thread SMT processor (SMT2) for a pair of threads saturated with floating point instructions. (Both of these last two comparisons make the assumption that the comparison processor possesses and equally wide and capable execution core, integer-wise and floating-point wise, respectively.)

Both CMT and SMT are at peak effectiveness while running integer and floating point code on a pair of threads. CMT stays at peak effectiveness while working on a pair threads consisting both of integer code, while under SMT, one or both threads will underperform due to competition for integer execution units. The disadvantage for CMT is a greater number of idle integer execution units in a single threaded case. In the single threaded case, CMT is limited to use at most half of the integer execution units in its module, while SMT imposes no such limit. A large SMT core with integer circuitry as wide and fast as two CMT cores could in theory have momentarily up to twice an integer performance in a single thread case. (More realistically for general code as a whole, Pollack's Rule estimates a speedup factor of 2{displaystyle {sqrt {2}}}, or approximately 40% increase in performance.)

CMT processors and a typical SMT processor are similar in their efficient shared use of the L2 cache between a pair of threads.

  • A module consists of a coupling of two 'conventional' x86 out of order processing cores. The processing core shares the early pipeline stages (e.g. L1i, fetch, decode), the FPUs, and the L2 cache with the rest of the module.
    • Each module has the following independent hardware resources:[12][13]
    • 16 KB 4-way of L1d (way-predicted) per core and 2-way 64 KB of L1i per module, one way for each of the two cores[14][15][16]
    • 2 MB of L2 cache per module (shared between the two integer cores)
    • Write Coalescing Cache[17] is a special cache that is part of L2 cache in Bulldozer microarchitecture. Stores from both L1D caches in the module go through the WCC, where they are buffered and coalesced. The WCC's task is reducing number of writes to the L2 cache.
    • Two dedicated integer cores
      • each one includes two ALU and two AGU which are capable of a total of four independent arithmetic and memory operations per clock and per core
      • duplicating integer schedulers and execution pipelines offers dedicated hardware to each of two threads which double performance for multi-threaded integer loads
      • the second integer core in the module increases the Bulldozer module die by around 12%, which at chip level adds about 5% of total die space[18]
    • Two symmetrical 128-bit FMAC (fused multiply–add capability) floating-point pipelines per module that can be unified into one large 256-bit-wide unit if one of the integer cores dispatches AVX instruction and two symmetrical x87/MMX/SSE capable FPPs for backward compatibility with SSE2 non-optimized software. Each FMAC unit is also capable of division and square root operations with variable latency.
  • All modules present share the L3 cache as well as an Advanced Dual-Channel Memory Sub-System (IMC – Integrated Memory Controller).
  • A module has 213 million transistors in an area of 30.9 mm² (including the 2 MB shared L2 cache) on an Orochi die.[19]
  • The pipeline depth of Bulldozer (as well as Piledriver and Steamroller) is 20 cycles, compared to 12 cycles of the K10 core predecessor.[20]

The longer pipeline allowed the Bulldozer family of processors to achieve a much higher clock frequency compared to its K10 predecessors. While this increased frequencies and throughput, the longer pipeline also increased latencies and increased branch misprediction penalties.

  • The width of the Bulldozer integer core, four (2 ALU, 2 AGU), is somewhat less than the width of the K10 core, six (3 ALU, 3 AGU). Bobcat and Jaguar also used a four wide integer core, yet with lighter execution units: 1 ALU, 1 simple ALU, 1 load AGU, 1 store AGU.[21]

The issue widths (and peak instruction executions per cycle) of a Jaguar, K10, and Bulldozer core are 2, 3, and 4 respectively. This made Bulldozer a more superscalar design compared to Jaguar/Bobcat. However, due to K10's somewhat wider core (in addition to the lack of refinements and optimizations in a first generation design) the Bulldozer architecture typically performed with somewhat lower IPC compared to its K10 predecessors. It was not until the refinements made in Piledriver and Steamroller, that the IPC of the Bulldozer family distinctly began to exceed that of K10 processors such as Phenom II.

Branch predictor[edit]

  • Two-level Branch Target Buffer(BTB)[22]
  • Hybrid predictor for conditionals
  • Indirect predictor

Instruction set extensions[edit]

  • Support for Intel's Advanced Vector Extensions (AVX) instruction set, which supports 256-Bit floating point operations, and SSE4.1, SSE4.2, AES, CLMUL, as well as future 128-bit instruction sets proposed by AMD (XOP, FMA4, and F16C),[23] which have the same functionality as the SSE5 instruction set formerly proposed by AMD, but with compatibility to the AVX coding scheme.

Process technology and clock frequency[edit]

  • 11-metal layer 32 nm SOI process with implemented first generation GlobalFoundries's High-K Metal Gate (HKMG)
  • Turbo Core 2 performance boost to increase clock frequency up to 500 MHz with all threads active (for most workloads) and up to 1 GHz with the half of the thread active, within the TDP limit.[24]
  • The chip operates at 0.775 to 1.425 V, achieving clock frequencies of 3.6 GHz or more[19]
  • Min-Max TDP: 25 – 140 watts

Cache and memory interface[edit]

  • Up to 8 MB of L3 shared among all cores on the same silicon die (8 MB for 4 cores in Desktop segment and 16 MB for 8 cores in the Server segment), divided into four subcaches of 2 MB each, capable of operating at 2.2 GHz at 1.1125 V[19]
  • Native DDR3 memory support up to DDR3-1866[25]
  • Dual Channel DDR3 integrated memory controller for Desktop and Server/Workstation Opteron 42xx 'Valencia';[26] Quad Channel DDR3 Integrated Memory Controller[27] for Server/Workstation Opteron 62xx 'Interlagos'
  • AMD claims support for two DIMMs of DDR3-1600 per channel. Two DIMMs of DDR3-1866 on a single channel will be down-clocked to 1600.

I/O and socket interface[edit]

  • HyperTransport Technology rev. 3.1 (3.20 GHz, 6.4 GT/s, 25.6 GB/s & 16-bit wide link) [first implemented into HY-D1 revision 'Magny-Cours' on the socket G34 Opteron platform in March 2010 and 'Lisbon' on the socket C32 Opteron platform in June 2010]
  • Socket AM3+ (AM3r2)
    • 942-pin, DDR3 support only
    • Will retain backward compatibility with Socket AM3 motherboards (as per motherboard manufacturer choice and if BIOS updates are provided[28][29]), however this not officially supported by AMD; AM3+ motherboards will be backward-compatible with AM3 processors.[30]
  • For the server segment, the existing socket G34 (LGA1974) and socket C32 (LGA1207) will be used.

Processors[edit]

Main articles: List of AMD FX microprocessors, List of AMD Accelerated Processing Unit microprocessors, and Opteron

The first revenue shipments of Bulldozer-based Opteron processors was announced on September 7, 2011.[31] The FX-4100, FX-6100, FX-8120 and FX-8150 were released in October 2011; with remaining FX series AMD processors released at the end of the first quarter of 2012.

Desktop[edit]

ModelCores/ModulesFrequencyMax. turboL2 cacheL3 cacheTDPMemoryTurbo CoreSocket
Full loadHalf load
FX-81008/42.8 GHz3.1 GHz3.7 GHz4 × 2 MB8 MB95 WDDR3
1866 MHz
Yes (2.0)AM3+
FX-81203.1 GHz3.4 GHz4.0 GHz125 W
FX-81403.2 GHz3.6 GHz4.1 GHz95 W
FX-81503.6 GHz3.9 GHz4.2 GHz125 W
FX-81703.9 GHz4.2 GHz4.5 GHz
FX-61006/33.3 GHz3.6 GHz3.9 GHz3 × 2 MB95 W
FX-61203.6 GHz3.9 GHz4.2 GHz
FX-61303.6 GHz3.8 GHz3.9 GHz
FX-62003.8 GHz4.0 GHz4.1 GHz125 W
FX-41004/23.6 GHz3.7 GHz3.8 GHz2 x 2 MB95 W
FX-41203.9 GHz4.0 GHz4.1 GHz
FX-41303.8 GHz3.9 GHz4.0 GHz4 MB125 W
FX-41503.8 GHz3.9 GHz4.0 GHz8 MB95/125 W
FX-41704.2 GHz4.3 GHz4.3 GHz125 W

Major Sources: CPU-World[32] and Xbit-Labs[33]

Server[edit]

There are two series of Bulldozer-based processors for servers: Opteron 4200 series (Socket C32, code named Valencia, with up to four modules) and Opteron 6200 series (Socket G34, code named Interlagos, with up to 8 modules).[34][35]

False advertising lawsuit[edit]

In November 2015, AMD was sued under the California Consumers Legal Remedies Act and Unfair Competition Law for allegedly misrepresenting the specifications of Bulldozer chips. The class-action lawsuit, filed on 26 October in the US District Court for the Northern District of California, claims that each Bulldozer module is in fact a single CPU core with a few dual-core traits, rather than a true dual-core design.[36]

Performance[edit]

Performance on Linux[edit]

On 24 October 2011, the first generation tests done by Phoronix confirmed that the performance of Bulldozer CPU was somewhat less than expected.[37] In many tests the CPU has performed on same level as older generation Phenom 1060T.

The performance later substantially increased, as various compiler optimizations and CPU driver fixes were released.[38][39]

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Performance on Windows[edit]

Copy

The first Bulldozer CPUs were met with a mixed response. It was discovered that the FX-8150 performed poorly in benchmarks that were not highly threaded, falling behind the second-generation Intel Core i* series processors and being matched or even outperformed by AMD's own Phenom II X6 at lower clock speeds. In highly threaded benchmarks, the FX-8150 performed on par with the Phenom II X6, and the Intel Core i7 2600K, depending on the benchmark. Given the overall more consistent performance of the Intel Core i5 2500K at a lower price, these results left many reviewers underwhelmed. The processor was found to be extremely power-hungry under load, especially when overclocked, compared to Intel's Sandy Bridge.[40][41]

On 13 October 2011, AMD stated on its blog that 'there are some in our community who feel the product performance did not meet their expectations', but showed benchmarks on actual applications where it outperformed the Sandy Bridge i7 2600k and AMD X6 1100T.[42]

In January 2012, Microsoft released two hotfixes for Windows 7 and Server 2008 R2 that marginally improve the performance of Bulldozer CPUs by addressing the thread scheduling concerns raised after the release of Bulldozer.[43][44][45]

On 6 March 2012, AMD posted a knowledge base article stating that there was a compatibility problem with FX processors, and certain games on the widely used digital game distribution platform, Steam. AMD stated that they had provided a BIOS update to several motherboard manufacturers (namely: Asus, Gigabyte Technology, MSI, and ASRock) that would fix the problem.[46]

In September 2014, AMD CEO Rory Read conceded the Bulldozer design had not been a 'game-changing part', and that AMD had to live with the design for four years.[47]

In July 29, 2015 Microsoft released the Direct X 12 API (DX12) for its Windows 10 operating system. This API allows programmers to achieve greater parallelism, notably in graphics intensive game titles. DX12 titles make better use of the higher core counts and high thread count processor such as the Bulldozer family's FX-6300 and FX-8100 series chips, extending the usability of these systems under Windows 10.[48]

Overclocking[edit]

On 31 August 2011, AMD and a group of well-known overclockers including Brian McLachlan, Sami Mäkinen, Aaron Schradin, and Simon Solotko managed to set a new world record for CPU frequency using the unreleased and overclocked FX-8150 Bulldozer processor. Before that day, the record sat at 8.309 GHz, but the Bulldozer combined with liquid heliumcooling reached a new high of 8.429 GHz. The record has since been overtaken at 8.58 GHz by Andre Yang using liquid nitrogen.[49][50] On August 22, 2014 and using an FX-8370 (Piledriver), The Stilt from Team Finland achieved a maximum CPU frequency of 8.722 GHz.[51]

Revisions[edit]

Piledriver is the AMD codename for its improved second-generation microarchitecture based on Bulldozer. AMD Piledriver cores are found in Socket FM2Trinity and Richland based series of APUs and CPUs and the Socket AM3+ Vishera based FX-series of CPUs. Piledriver was the last generation in the Bulldozer family to be available for socket AM3+ and to be available with an L3 cache. The Piledriver processors available for FM2 (and its mobile variant) sockets did not come with a L3 cache, as the L2 cache is the last-level cache for all FM2/FM2+ processors. Wonderware intouch 2012 r1 download.

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Steamroller is the AMD codename for its third-generation microarchitecture based on an improved version of Piledriver. Steamroller cores are found in the Socket FM2+Kaveri based series of APUs and CPUs.

Excavator is the codename for the fourth-generation Bulldozer core.[52]Excavator was implemented as 'Carrizo' A-series APUs, and Athlon x4 CPUs. [53]

See also[edit]

References[edit]

  1. ^'FX Processors'. AMD. 24 February 2016. Retrieved 24 February 2016.
  2. ^'AMD ships 16 core bulldozer powered Opteron 6200'. Engadget. 14 November 2011. Retrieved 24 February 2016.
  3. ^Bulldozer 50% Faster than Core i7 and Phenom II, techPowerUp, retrieved 2012-01-23
  4. ^AMD64 Architecture Programmer’s Manual Volume 6: 128-Bit and 256-Bit XOP, and FMA4 Instructions(PDF), AMD, May 1, 2009, retrieved 2009-05-08
  5. ^Striking a balance, Dave Christie, AMD Developer blogs, 7 May 2009, retrieved 2009-05-08
  6. ^AMD Sets New Mark in x86 Innovation with First Detailed Disclosures of Two New Core Designs, AMD, August 24, 2011, p. 1, retrieved September 18, 2011
  7. ^Analyst Day 2009 Summary, AMD, November 11, 2009, retrieved 2009-11-14
  8. ^AMD bestätigt: 'Zambezi' ist inkompatibel zum Sockel AM3, Planet3dnow.de, retrieved 2012-01-23
  9. ^Analyst Day 2009 Presentations, AMD, November 11, 2009, retrieved 2009-11-14
  10. ^http://cdn3.wccftech.com/wp-content/uploads/2013/07/AMD-Steamroller-vs-Bulldozer.jpg
  11. ^'AMD unveils Flex FP - bit-tech.net'. bit-tech.net.
  12. ^Bulldozer microarchitecture block, AnandTech, August 24, 2010
  13. ^Bulldozer module functional schematic, AMD, August 24, 2010
  14. ^More On Bulldozer, Tomshardware.com, 2010-08-24, retrieved 2012-01-23
  15. ^AMD Reveals Details About Bulldozer Microprocessors, AMD Reveals Details About Bulldozer Microprocessors, Xbitlabs.com, retrieved 2012-01-23
  16. ^Real World Technologies (2010-08-26), AMD's Bulldozer Microarchitecture, Realworldtech.com, retrieved 2012-01-23
  17. ^David Kanter (August 26, 2010). 'AMD's Bulldozer Microarchitecture Memory Subsystem Continued'. Real World Technologies.
  18. ^Bulldozer design power efficiency, AMD, August 24, 2010
  19. ^ abcAP(PDF), retrieved 2012-01-23
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External links[edit]

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